A conventional metal oxide semiconductor field effect transistor (MOSFET) utilizes heavily doped source and drain semiconductor regions to form ohmic contacts to a gate induced inversion-layer channel portion. In the on-state, transport in this channel portion controls the source-drain current, IDS. In the on-state, the inverted channel is not shunted due to the presence of a reversed-biased n/p or p/n junction at the drain. In the off-state there is no inversion in the channel portion and the current, ID is blocked by the reverse biased n/p or p/n junction at the drain. The thin film transistor (TFT) is a variant of the MOSFET in which an on-state conducting channel is also not shunted but, in this case, due to a reversed bias i/n or i/p junction at the drain which is in series with the additional impediment of the thin, resistive i-layer under the gate. Both TFTs and MOSFETs are types of field effect transistor (FET) structures.
A typical FET device includes a gate, drain, and source. Typically, the gate is used to control the device by applying an adequate voltage to the gate to generate an electric field that in turn creates a conductive path in an underlying channel layer intermediate between the drain and source. A device in which conduction exists between the source and drain is considered to be ins an on-state whereas a lack of conduction is considered as an off-state.
The gate, the third terminal of these devices, needs to be electrically isolated from the channel layer. To achieve electrical isolation of the gate, a dielectric material such as silicon dioxide is provided intermediate between the gate and the underlying channel layer. To improve device characteristics it is often desired to reduce the dielectric (insulator) layer thickness to increase gate capacitance and improve gate to channel coupling. An inverse proportionality exists for MOSFET and TFT type devices between the gate capacitance and insulating layer thickness. Unfortunately, reducing insulating layer thickness beyond a certain point has proven difficult as gate leakage current outweighs any benefits achieved through gate capacitance increases.
The trend in microelectronics is to ever smaller devices since this allows for faster operating speeds and greater functionality per area. Fabricating such small devices can be costly since the processing involved generally necessitates multiple etching and deposition steps all guided by lithography. Nanowires, nanotubes, and nanoribbons are inherently small; hence there is a great deal of interest in fabricating FET devices using these materials.
FET structures that can be fabricated with the dimension normal to the gate being in the nanoscale include TFTs on ultra-thin semiconductors, SOI-type structures, thin-fin devices and nanowire devices. Among these possibilities, devices with a single doping type have been fabricated using nanowires (NWs) by Lieber et al.5,6,7, Mayer et al.8, and Yang et al.9 These have used semiconductor nanowires of a single doping type and concentration, ohmic source and drain contacts to this semiconductor, and metal/insulator gates and have been professed to be MOSFETs5,6,7,8,9. These prior art devices have stressed the importance of gate capacitance, CI in on-state operation. The prior art has not taught the role of doping concentration on on-state current, has not taught the importance of the position of ohmic contacts with respect to channel edges, the correct role of CI in on-state operation, nor the role of the doping concentration in the various regions of the transistor on performance of single doping-type FETs. The role of the voltage VDS developed between the source and drain in a single doping type structure has not be realized and there has been a lacking of guidance as to device design. In fact, Mayer et al. has strongly taught away from NW FET structures with single doping type citing that they are not capable of good on-current to off-current ratios nor of good subthreshold slopes (swing) values.8 Thus, there exists a need for a gated microstructure that is simple to fabricate and has straightforward design rules. Using a single doping type for the source, gate, and drain regions, as disclosed in this invention, is a major simplification step as is the disclosed use of substantially ohmic contacts to the source and drain regions. Further, having a FET device whose dependence on gate capacitance is weaker than that of a MOSFET overcomes the problem of the need for close fabrication control of the gate insulator. There also exists a need for a simplified formation of FET-type structure to advance the operation of microelctronics and macroelectronics (electronics applied to large areas).